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-- Company: 
-- Engineer:
--
-- Create Date:   11:42:31 03/04/2012
-- Design Name:   DataRegister
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_DataRegister.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DataRegister
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_DataRegister_vhd IS
END tb_DataRegister_vhd;

ARCHITECTURE behavior OF tb_DataRegister_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT DataRegister
	PORT(
		data_word_i : IN std_logic_vector(7 downto 0);
		port_word_i : IN std_logic_vector(7 downto 0);
		clk : IN std_logic;
		dr_sel : IN std_logic;
		data_sel : in STD_LOGIC;
		dataReg_o : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL dr_sel :  std_logic := '0';
	SIGNAL data_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL port_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL data_sel : std_logic := '0';

	--Outputs
	SIGNAL dataReg_o :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: DataRegister PORT MAP(
		data_word_i => data_word_i,
		port_word_i => port_word_i,
		clk => clk,
		dr_sel => dr_sel,
		data_sel => data_sel,
		dataReg_o => dataReg_o
	);

	clk <= not clk after 25 ns; --periodo 50 ns

	tb : PROCESS
	BEGIN
	
		data_sel <= '1';
		wait for 49 ns;
		dr_sel <= '0';
		
		port_word_i <= "00000000";
		data_word_i <= "11111111";
		assert (dataReg_o /= "11111111")
			report "ERROR EN LA LECTURA DE DATOS"
			severity FAILURE;
			
		data_sel <= '0';		
		wait for 50 ns;
		dr_sel <= '1';		
		
		assert (dataReg_o /= "11111111")
			report "ERROR EN HABILITACION DE dr_sel"
			severity FAILURE;
		
		wait for 50 ns;
		data_sel <= '1';
		assert (dataReg_o /= "00000000")
			report "ERROR EN LA LECTURA DE PUERTOS"
			severity FAILURE;
		
						
		 report ("**********TESTS DE DATA REGISTER SUPERADOS**********")
		 severity NOTE;
		wait; -- will wait forever
	END PROCESS;

END;
